Compute Express Link (CXL) 2.0 Controller with AMBA AXI interface
DDR4/3/3L/LPDDR3 Combo PHY & Controller
Note that all INNOSILICON PHY is pre-assembled with.lib, LEF and GDS so that it is very easy to integrate the PHY with any existing SoC floor plan. DDRn bus width can be from 4 bit to 72 bit or more. INNOSILICON is happy to pre-assemble each PHY for our customer so that integration becomes extremely easy.
The combo PHY solution includes DDRn controller and PHY, supporting DDR4/3/3/LPDDR3. With configurable timing and driving strength parameters to interface to the wide variety of SDRAMs, the PHY is very flexible with advanced command capability to increase SDRAM operation efficiency.
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