DDR4/3/3l PHY UMC22ULP

The INNOSILICON DDR IPTM Mixed-Signal DDR4/DDR3/DDR3L combo PHY provides turnkey physical interface solutions for ICs requiring access to JEDEC compatible SDRAM devices. It is optimized for low power and high speed (up to 2400Mbps) applications with robust timing and small silicon area in 22nm process. It supports JEDEC DDR4/DDR3/DDR3L SDRAM components in the market. The PHY components contain DDR specialized functional and utility, critical timing synchronization module (TSM) and a low power/jitter PLLs for SDRAM interface.

• see the entire DDR4/3/3l PHY UMC22ULP datasheet
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