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DDR4/3/4l/3l PHY TSMC12FFC
The INNOSILICON DDR IPTM Mixed-Signal DDR4/DDR3/DDR3L combo PHY provides turnkey physical interface solutions for ICs requiring access to JEDEC compatible SDRAM devices. It is optimized for low power and high speed (up to 2400Mbps) applications with robust timing and small silicon area in 22nm process. It supports JEDEC DDR4/DDR3/DDR3L SDRAM components in the market. The PHY components contain DDR specialized functional and utility, critical timing synchronization module (TSM) and a low power/jitter PLLs for SDRAM interface.
Features
- DDR4/DDR3/DDR3L modes & signaling，rates from 100Mbps up to 2400Mbps
- x16/x32 data path interface extendable
- 1.2V POD JEDEC and 1.5V/1.35V SSTL standard IOs
- Multiple drive strengths adjustable
- Independent read and write timing adjustments with auto calibration
- Low latency with programmable timings for secure data handling
- Per bit deskew support
Benefits
- Fully pre-assemble design, Drop-in hard macro to ease integration and speed time to market,
- Zero risk with robust ESD architecture
- Maintains self-refresh I/O drive state during VDD power down
- Extensive EDA tool support for various design automation flows
- Optional CKE retention mode permits VDD and all non-essential I/Os to be powered down while retaining the external SDRAMs in self refresh mode
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