Cortex-X4, Ultimate Performance for Next-Generation Smartphones and Laptops
DDR4/3 PHY in Samsung (14nm, 10nm, 8nm)
Optimized for high performance, low latency, low area, low power, and ease of integration, the DesignWare DDR4/3 PHY is provided as a hard DDR PHY that is primarily delivered as GDSII including integrated application-specific DDR4/3 I/Os. Supporting the GDSII-based PHY is the RTL-based PHY Utility Block (PUB) that includes PHY control features such as read/write leveling, data eye training, per-bit data deskew control, PVT compensation, and support for production testing of the DDR4/3 PHY. The PUB also includes an embedded calibration processor to execute hardware-assisted, firmware-based training algorithms. The DDR4/3 PHY includes a DFI 4.0 interface to the memory controller and can be combined with Synopsys’ Enhanced Universal Memory (uMCTL2) or Protocol (uPCTL2) controllers for a complete DDR interface solution.
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Video Demo of the DDR4/3 PHY in Samsung (14nm, 10nm, 8nm)
SDRAMs such as DDR, LPDDR, and HBM offer unique advantages for automotive, artificial intelligence (AI), cloud, and mobile applications. However, the selected memory solution impacts the performance, power, and area requirements of SoCs, making it important to choose the right memory technology and interface IP for the target design. Meet your specific design targets by using Synopsys’ high-performance, silicon-proven DDR memory interface IP solutions compliant with the latest JEDEC standards.