The Cadence Denali Controller IP for DDR4 is a highly configurable DDR design that provides the high flexibility needed to enable application specific configurations ranging from high performance networking and mobile to consumer.
It includes sophisticated engines to rearrange transactions and maximize memory bus utilization. Programmable arbitration algorithms allow for multiple ports to share the memory bus efficiently. The Denali Controller IP for DDR4 is configurable to meet specific data profiles and enables performance optimization for an individual system and memory requirements.
- Compliant to LPDDR 4/3 and DDR 4/3/3L protocol memories
- Single and multi-port host interface options
- Flexible paging policy including auto-precharge-per-command
- Supports advanced RAS features including SEC/DED ECC, error scrubbing, parity, etc
- Priority-per command on ARM(R) AMBA(R)3 AXI and low latency Denali interface
- QoS features allow command prioritization on ARM AMBA4 AXI interfaces
- Silicon proven and shipping in volume
- Configurable to meet specific data traffic profiles
- Optimized low latency for data-intensive applications
- Future-proof system design for emerging DDR standards
- Clean, readable, synthesizable Verilog RTL
- Synthesis and STA scripts
- Documentation: integration and user guide, release notes
- Sample Verification testbench with integrated BFM and monitors