English
You are here:
DDR5 Controller and PHY
Cadence has prototyped the world’s first IP interface in silicon for a preliminary version of DDR5 standard. A test chip contains the next-generation memory interface IP based on the industry consensus of what is likely to be in the DDR5 standard, and Micron has supplied prototype DRAM chips. The test chip was fabricated in a 7nm process and contains both the controller and PHY. The prototype successfully achieves 4400 megatransfers per second, 37.5% faster than the fastest commercially available DDR4 memory.
Features
- Silicon-proven DRAM interoperability at 4400 MT/s
- Lowest-latency DDR controller and PHY IP
- Extremely flexible in configuration and PHY placement with Firm PHY model
- Advanced DDR PHY clocking architecture minimizes clock jitter
Benefits
- Configurable to meet specific data traffic profiles
- Optimized low latency for data-intensive applications
- Future-proof system design for emerging DDR standards
Deliverables
- Documentation including integration and user guide, release notes
- Clean, readable, synthesize-able Verilog RTL
- Synthesis and STA scripts
- GDS II macros with abstract in LEF
- Liberty Timing model
- Verilog testbench with memory model, configuration files, and sample tests
- Verification IP set up files
- SDF for back-annotated timing verification
- Verilog models of I/O pads, and RTL for all PHY modules
Applications
- High-performance computing
- Networking
View DDR5 Controller and PHY full description to...
- see the entire DDR5 Controller and PHY datasheet
- get in contact with DDR5 Controller and PHY Supplier
DDR5
- DDR5/4 PHY in TSMC (16nm, 7nm)
- DDR5 Controller and PHY
- DesignWare DDR5/4 PHY IP for TSMC N7
- PHY IP for HBM2 for Samsung 10LPP
- DDR and LPDDR 4/3/2 controllers for low power and high Reliability, Availability and Serviceability (RAS) targeting automotive
- DDR and LPDDR 4/3/2 controllers for low power and high Reliability, Availability and Serviceability (RAS)