DDR5 Controller and PHY

Cadence has prototyped the world’s first IP interface in silicon for a preliminary version of DDR5 standard. A test chip contains the next-generation memory interface IP based on the industry consensus of what is likely to be in the DDR5 standard, and Micron has supplied prototype DRAM chips. The test chip was fabricated in a 7nm process and contains both the controller and PHY. The prototype successfully achieves 4400 megatransfers per second, 37.5% faster than the fastest commercially available DDR4 memory.

• see the entire DDR5 Controller and PHY datasheet
• get in contact with DDR5 Controller and PHY Supplier