Design & Reuse
Catalog of SIP Cores
Silicon on Chip design resources

DDR5/DDR4/LPDDR5 Combo PHY IP - 4800Mbps (Silicon Proven in TSMC 12FFC)

The DDR PHY IP supports DDR5/ DDR4/ LPDDR5, provides low latency, and enables up to 5400MT/s throughput. PHY functionality is verified in NC-Verilog s...