So_ip_idte core can be used create an ensemble of decision trees directly in hardware. DTs that make up the ensemble can have univarite, multivariate and non-linear tests. Creating DT ensemble directly in hardware results in the significant increase of the inference speed, compared with the traditional software-based approach.
So_ip_idte core uses bagging algorithm to create a DT ensemble. Bagging is one of the earliest proposed ensemble-creation algorithms. It is also one of the most intuitive and simplest to implement, with surprisingly good performance. Bagging is particularly appealing when the available data is of limited size. Bagging algorithm can be easily parallelized in contrast to most other popular methods for the ensemble classifier creation. At the hart of the bagging algorithm a proprietary DT inference algorithm based on the evolutionary algorithms, developed at So-Logic, is used to infer individual DT members in parallel. This approach results in very fast DT ensemble inference times while still having acceptable resource requirements.
After the inference process is complete, complete structural information about the created DTs is transferred through the output ports. This information can be easily transferred to some of the So-Logic’s DT ensemble evaluation cores enabling hardware implementation of the inferred DT ensemble. By combining these two cores a hardware-based adaptive learning ensemble systems can be easily designed.
So_ip_idte core is delivered with fully automated testbench and a compete set of tests allowing easy package validation at each stage of SoC design flow.
The so_ip_idte design is strictly synchronous with positive-edge clocking, no internal tri-states and a synchronous reset.
The so_ip_idte core can be evaluated using any evaluation platform available to the user before actual purchase. This is achieved by using a time-limited demonstration bit files for selected platform that allows the user to evaluate system performance under different usage scenarios.