So_ip_edte_smpl_p core can be used to implement the ensemble member evaluation module as a part of an ensemble classifier consisting from decision tree with the previously defined structure directly in hardware. It implements every DT from the ensemble as a separate module using an advanced pipelined architecture that allows the fastest possible classification speed.
So_ip_edte_smpl_p core is delivered with fully automated testbench and a compete set of tests allowing easy package validation at each stage of SoC design flow.
The so_ip_edte_smpl_p design is strictly synchronous with positive-edge clocking, no internal tri-states and a synchronous reset.
The so_ip_edte_smpl_p core can be evaluated using any evaluation platform available to the user before actual purchase. This is achieved by using a time-limited demonstration bit files for selected platform that allows the user to evaluate system performance under different usage scenarios.