Rambus DPA Resistant Cryptographic Accelerator Core ChaCha20 – Small
Decision tree evaluation core using pipelined architecture
So_ip_edt_smpl core is delivered with fully automated testbench and a compete set of tests allowing easy package validation at each stage of SoC design flow.
So_ip_edt_smpl design is strictly synchronous with positive-edge clocking, no internal tri-states and a synchronous reset.
So_ip_edt_smpl core can be evaluated using any evaluation platform available to the user before actual purchase. This is achieved by using a time-limited demonstration bit files for selected platform that allows the user to evaluate system performance under different usage scenarios.
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