So_ip_edt_smpl core can be used to implement the decision tree with the previously defined structure directly in hardware. It uses advanced pipelined architecture that allows the fastest possible classification speed.
So_ip_edt_smpl core is delivered with fully automated testbench and a compete set of tests allowing easy package validation at each stage of SoC design flow.
So_ip_edt_smpl design is strictly synchronous with positive-edge clocking, no internal tri-states and a synchronous reset.
So_ip_edt_smpl core can be evaluated using any evaluation platform available to the user before actual purchase. This is achieved by using a time-limited demonstration bit files for selected platform that allows the user to evaluate system performance under different usage scenarios.
- Implements DTs with previously defined structure
- Uses advanced pipelined architecture that allows the fastest possible classification speed
- Supports classification problems that are defined by numerical attributes only
- DTs with univariate or multivariate tests are supported
- DTs with nonlinear tests are supported
- Possibility to alter the implemented DT structure during the actual operation
- No special IP blocks are needed to implement the core, only memory, adders and multipliers
- User can specify the number format for all DT parameters in order to achieve the best performance/size ratio after implementation
- VHDL Source Code or netlis
- Verification environment with regression suite
- Technical documentation
- Installation notes
- User Manual
- Instantiation templates
- Reference Design
- Technical Support
- IP Core implementation support
- Variable length maintenance
- Delivery of IP Core updates, minor and major changes
- Delivery of documentation updates
- Telephone & email support