So_ip_idt core can be used create a decision tree directly in hardware. It can create DTs with univarite, multivariate and non-linear tests. Creating DTs directly in hardware results in the significant increase of DT inference speed, compared with the traditional software-based approach.
So_ip_idt core implements a proprietary DT inference algorithm based on the evolutionary algorithms, developed at So-Logic, that enables quick DT inference with very favorable DT characteristics (measured in terms of inferred DT size and accuracy) when compared with the existing popular DT inference algorithms (C5, CART, etc.).
After the inference process is complete, complete structural information about the created DT is transferred through the output port. This information can be easily transferred to some of the So-Logic’s DT evaluation cores enabling hardware implementation of the inferred DT. By combining these two cores a hardware-based adaptive learning systems can be easily designed.
So_ip_idt core is delivered with fully automated testbench and a compete set of tests allowing easy package validation at each stage of SoC design flow.
The so_ip_idt design is strictly synchronous with positive-edge clocking, no internal tri-states and a synchronous reset.
The so_ip_idt core can be evaluated using any evaluation platform available to the user before actual purchase. This is achieved by using a time-limited demonstration bit files for selected platform that allows the user to evaluate system performance under different usage scenarios.
- Enables DT creation directly in hardware
- Speedup of inference time of over 1000x compared to the traditional software approach
- Supports classification problems that are defined by numerical attributes only
- DTs with univariate or multivariate tests are supported
- DTs with nonlinear tests are supported
- No special IP blocks are needed to implement the core, only memory, adders and multipliers
- User can specify the number format for all DT parameters in order to achieve the best performance/size ratio after implementation
- Can be easily integrated with some of the So-Logic’s DT evaluation cores to create hardware-based adaptive learning systems
- VHDL Source Code or netlis
- Verification environment with regression suite
- Technical documentation
- Installation notes
- User Manual
- Instantiation templates
- Reference Design
- Technical Support
- IP Core implementation support
- Variable length maintenance
- Delivery of IP Core updates, minor and major changes
- Delivery of documentation updates
- Telephone & email support