The customizable EXOSTIV IP core is a logic analyzer core that can be used to monitor the internal signals of an FPGA design without having to store the full trace data in the FPGA. The EXOSTIV IP core uses the FPGA transeivers as a high bandwidth channel to an external memory (in EXOSTIV Probe). The IP includes many advanced features for extending visibility on FPGA running at speed of operation- including data group definition and multiplexing, boolean trigger equations, data qualification (data filtering) and edge transition triggers. Because EXOSTIV IP core is synchronous to the design being monitored, all design clock constraints that are applied to your design are also applied to the components inside IP Core. EXOSTIV IP is at RTL level thanks to IP templates and constraints automatically generated at IP setup.
- Configurable upstream link, up to 4 transceivers at 12.5 Gbps each.
- Downstream link to configure IP triggers and data group selection without the need to re-implement the instrumented design.
- Up to 16 configurable 'Capture Units'
- Up to 16 multiplexed Data Groups per Capture Unit
- Up to 2,048 nodes per Data Group
- Up to 32k simultaneously observable nodes
- Multi-clock domain support
- Cross-capture unit trigger lines
- Extreme visibility on FPGA running at speed of operation
- Efficient use of FPGA resources: the size of the IP memory in the FPGA does not grow with the size of the capture.
- Extended visibility over time: the capture can span to hours of real FPGA operating times, from start to end (interrupted capture mode)
- Real-world visibility level with a total of 8 GB of trace for a single capture.
- Complete FPGA debugging solution, including EXOSTIV Dashboard software (Linux, Windows) for EXOSTIV IP setup and insertion - and for EXOSTIV IP control for trace data extraction at run-time.
- Includes EXOSTIV Probe for data extraction from target FPGA at run-time.
- Includes terabyte-capable Myriad waveform viewer.
- FPGA debug and verification
Block Diagram of the Deep capture / high visibility Debug IP for Intel FPGA