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Dual thread, superscalar, embedded 32-bit RISC-V core with 9-stage pipeline
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Deinterlacer
The Deinterlacer IP core converts input video stream from interlaced format into progressive format and uses bob, intra and inter motion adaptive deinterlacing algorithms to reduce interline flicker and jagged edge. The Deinterlacer IP core supports YCbCr4:2:2, YCbCr4:4:4 and RGB format, serial and parallel deinterlacing. The Deinterlacer IP core provides a parameter bus for dynamic parameters updating and the parameter bus can be configured running at a separate clock. Also it supports a simple frame rate conversion function.
Interlaced video frames consists of two sequent fields, which are scanned at even and odd lines of the image sensor. Interlaced video has less transmission bandwidth, but most modern displays support progressive frame only. The two interlaced fields must be converted to one progressive frame for display, which is known as deinterlacing. As the two interlaced fields are taken at different time, there will be flicker and jagged edges in the combined frame. A good deinterlacing algorithm should reduce these artifacts as much as possible and provide good video quality in the process. Lattice Deinterlacer IP core provides several deinterlacing algorithms for different video quality and resource: weave, bob, intra and inter motion adaptive deinterlacing algorithms.
Interlaced video frames consists of two sequent fields, which are scanned at even and odd lines of the image sensor. Interlaced video has less transmission bandwidth, but most modern displays support progressive frame only. The two interlaced fields must be converted to one progressive frame for display, which is known as deinterlacing. As the two interlaced fields are taken at different time, there will be flicker and jagged edges in the combined frame. A good deinterlacing algorithm should reduce these artifacts as much as possible and provide good video quality in the process. Lattice Deinterlacer IP core provides several deinterlacing algorithms for different video quality and resource: weave, bob, intra and inter motion adaptive deinterlacing algorithms.
Features
- Supports for single color, YCbCr4:2:2, YcbCr4:4:4 and RGB video formats.
- Supports serial and parallel deinterlacing.
- Supports weave, bob, intra and inter motion adaptive deinterlacing algorithms.
- Supports frame rate conversion.
- Configurable initial field.
- Configurable thresholds for inter motion adaptive deinterlacing algorithm.
- Dynamic parameters updating: frame size, initial field and bypass mode.
- Configurable parameter bus width.
- Configurable separate parameters bus clock.
- Configurable memory bus width and base address.
- Configurable burst length and burst count.
- Configurable internal FIFO type and depth.
- Configurable pixel data width.
- Configurable line buffer type.
Block Diagram of the Deinterlacer IP Core
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