Provides the industry's highest data rates with low-latency througput while balancing power consumption and minimizing area
Developed by experienced teams with industry-leading domain expertise and extensively validated with multiple hardware platforms, the DDR PHY IP is silicon-proven and can provide customers with ease of integration and faster time to market. The DDR PHY IP is engineered to quickly and easily integrate into any system on chip (SoC), and is verified with the Denali DDR controller IP as part of a complete memory subsystem solution. The DDR PHY IP is designed to connect seamlessly and work with a thirdparty DFI-compliant memory controller. The DDR PHY IP is developed and validated to reduce the risk for the customer so that their SoC can be first-time right. Developed for and available early in the lifecycle of the most advanced semiconductor process nodes, the DDR PHY IP is designed to be robust under varying noise conditions and to have interoperability with various supplier memory chips. The DDR PHY IP is part of the comprehensive Cadence Design IP portfolio comprised of an interface, Denali memory interface, analog, and systems and peripherals IP.