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CXL Controller
The DesignWare® Compute Express Link (CXL) Controller IP implements the port logic required to build a CXL device or host, and can be configured for dual mode applications. The configurable and scalable IP supports all required features of the CXL 1.0 and 1.1 specifications, as well as PCI Express 5.0, 4.0, and 3.1 specifications, and can be easily connected to a DesignWare 32 GT/s PHY through the built-in PIPE 5.2 interface. The high-quality, synthesizable IP is optimized for maximum throughput and minimum latency in a 32 GT/s x16 configuration, but can be configured to support CXL port bifurcation and degraded modes, as well as all 3 defined CXL device types for maximum application flexibility. The DesignWare CXL Controller IP integrates quickly and easily into system-on-chip (SoC) designs with a user-friendly application interface or an industry standard AMBA interface on the CXL.io side, with conservative timing suitable for a wide range of ASIC and FPGA technologies. The DesignWare CXL Controller IP is based on the Synopsys PCI Express controller IP which has been silicon validated in over 1700 designs with multiple hardware platforms, PHYs, and PCI Express verification suites, thereby reducing risk and accelerating time-to-market. As the industry standard for PCI Express, Synopsys offers a comprehensive IP solution that is in volume production and has been successfully implemented in a wide range of applications.
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Block Diagram of the CXL Controller
Video Demo of the CXL Controller
Gary Ruggles, senior staff product marketing manager at Synopsys, talks with Semiconductor Engineering about the Compute Express Link standard, why it’s important for high bandwidth in AI/ML applications, where it came from, and how to apply it in current and future designs