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CXL Controller
The DesignWare® Compute Express Link (CXL) Controller IP implements the port logic required to build a CXL device or host, and can be configured for dual mode applications. The configurable and scalable IP supports all required features of the CXL 1.0 and 1.1 specifications, as well as PCI Express 5.0, 4.0, and 3.1 specifications, and can be easily connected to a DesignWare 32 GT/s PHY through the built-in PIPE 5.2 interface. The high-quality, synthesizable IP is optimized for maximum throughput and minimum latency in a 32 GT/s x16 configuration, but can be configured to support CXL port bifurcation and degraded modes, as well as all 3 defined CXL device types for maximum application flexibility. The DesignWare CXL Controller IP integrates quickly and easily into system-on-chip (SoC) designs with a user-friendly application interface or an industry standard AMBA interface on the CXL.io side, with conservative timing suitable for a wide range of ASIC and FPGA technologies. The DesignWare CXL Controller IP is based on the Synopsys PCI Express controller IP which has been silicon validated in over 1700 designs with multiple hardware platforms, PHYs, and PCI Express verification suites, thereby reducing risk and accelerating time-to-market. As the industry standard for PCI Express, Synopsys offers a comprehensive IP solution that is in volume production and has been successfully implemented in a wide range of applications.
Features
- Fully supports the CXL 1.0 and 1.1 specifications
- Supports PCI Express 5.0 mode with 32 GT/s and x16 link width
- Fully supports PCI Express 5.0 base specification revision 1.0
- Supports PIPE 5.X Interface for connection to 32 GT/s PCI Express 5.0 PHYs
- PCIe/CXL.io Application interface with the Synopsys native interface or the optional Arm AMBA 4 AXI and AMBA 3 AXI
- Supports operation at x16 and x8, and degraded modes at x4, x2, and x1
- CXL host and device support, with dual mode capability to enable DUT-to-DUT testing
- Implements CXL.io, CXL.mem, and CXL.cache protocols
- Supports all 3 defined CXL device types for maximum design flexibility
- High-speed CXL.cache/mem interfaces for minimum latency
- Highly efficient flit-packing algorithm
- Optional Drift buffer for reduced latency
- Multiple CXL.cache device to host request and Response interfaces to maximize throughput
- Multiple CXL.mem Subordinate to Master Response/No Response channels for enhanced throughput
- Supports Data Poisoning by transmitter
- Address Translation Services (ATS)
- PCI Express Advanced Error Reporting (AER)
- Supports deferrable writes
- Removal of sync header from Ordered set blocks in latency optimized mode.
- Supports PCI Express Alternate Protocol
- PCI Express Port, Device, and Compliance Designated Vendor-Specific Extended Capabilities (DVSEC) for CXL.
- CXL upstream port RCRB with registers from PCI Express upstream ports, configuration header and PCI Express capabilities
- CXL upstream port MEMBAR0
- FLR support for CXL.io
- Supports CXL containment feature (“Viral”)
- Industry-leading Reliability, Availability and Serviceability (RAS) features extended to support new CXL features
- Selected PCIe 5.0 supported features: – Supports all required features of the PCI Express 5.0, 4.0, 3.1, 2.1, and 1.1 specifications – Full transaction layer, data link layer and physical layer – Supports up to sixteen 32.0, 16.0, 8.0, 5.0, 2.5 GT/s lanes (CXL supports only 8.0, 16.0 and 32.0 GT/s data rates) – Available in 512-bit datapath width – Optional embedded DMA controller with up to 8 read and 8 write channels for high-throughput with minimal SoC resource overhead – Supports optional ECNs
Benefits
- DesignWare Controller IP for PCI Express provides a complete set of features which enable the user to define an optimized PCI Express interface in products across the full spectrum of applications. With PCI Express storage dominating today’s client and enterprise markets, the DesignWare Dual Mode Controller IP for PCI Express supports PCI Express features critical to effective implementations of these and other products requiring extreme robustness:
- Ultra low transmit and receive latency and high accessible bandwidth
- RAS data protection providing ECC and/or parity protection for internal busses and memories
- Advanced debug capabilities for error injection and statistical monitoring for PCI Express 5.0 with CXL enhancements
- CXL.io supports ECRC and data poisoning
- CXL.mem/CXL.cache supports data poisoning and “Viral” error containment Building atop those features, the controller IP offers additional performance and virtualization features for a variety of enterprise class implementations:
- Supports multiple virtual channels and traffic classes
- Directly supports up to 32 physical functions and up to 256 virtual functions using SR-IOV and ARI – Optional extension up to 64K virtual functions
- Supports up to 256/768 outstanding PCI Express requests
Deliverables
- The coreConsultant utility to guide designers through the installation configuration, verification, and implementation of the IP
- Verilog RTL code
- Example PHY interfaces
- ASIC and FPGA synthesis scripts
- Verification environment
- Synopsys Verification IP for PCI Express
- Documentation: release notes, installation/integration guide, application notes, user manual
Applications
- AI/machine learning
- High-performance networking
- Media/graphics
- Memory expansion
- General purpose acceleration
Video Demo of the CXL Controller
Gary Ruggles, senior staff product marketing manager at Synopsys, talks with Semiconductor Engineering about the Compute Express Link standard, why it’s important for high bandwidth in AI/ML applications, where it came from, and how to apply it in current and future designs
View DesignWare CXL Controller IP full description to...
- see the entire DesignWare CXL Controller IP datasheet
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