Compact 32-bit MCU core for deeply embedded applications and accelerator control
DDR5/4 Controller IP with a CHI Interface
The DesignWare DDR5/4 Controller connects to the DesignWare DDR5/4 PHY or other PHYs via the DFI 5.0 interface to create a complete memory interface solution.
The controller includes software configuration registers, which are accessed through an AMBA 3.0 APB interface. The DDR controller block includes advanced command scheduler, memory protocol handler, optional ECC (Error-correcting code), and dual-channel support, as well as the DFI interface to the PHY.
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DDR5/4 Controller IP
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