DDR5/4 Controller with Advanced Features Package

Features

• Complete, integrated DDR solution from a single vendor when combined with Synopsys’ DesignWare DDR PHY IP
• Supports DDR5 and DDR4 memory protocol based SDRAMs and U/SO/R/LRDIMMs
• Up to 32 logical ranks
• DDR PHY Interface (DFI) support for easy integration with industry standard DFI 5.0 compliant PHYs
• 1:4 clock ratio for DDR5 with efficient phase-aware scheduling
• Up to 16 configurable AMBA ports (AXI4/AXI3)
• Enables system designers to extend QoS control into the memory controller
• Supports a host interface slave for easy integration with an external arbiter or non-AMBA on-chip buses Efficient DDR protocol implementation leveraging out-of-order transactions to maximize data throughput, while ensuring starvation avoidance and guaranteeing data coherency
• Read Reorder Buffer (RRB) substantially improves bandwidth while preserving AXI ordering rules Optional ECC module with scrubbing capability • APB interface for software accessible registers

Benefits

• Supports JEDEC standard DDR5 and DDR4 SDRAMs and DIMMs
• Multiport Arm® AMBA® interface (4 AXI™/3 AXI™) with managed QoS or single-port host interface to the DDR controller
• DFI 5.0 compliant interface to DesignWare DDR5/4 PHY or other DDR5/4 PHYs
• Best in class performance with unique features such as QoS-based scheduling and phase-aware scheduling
• High-bandwidth design with up to 64 CAM entries for reads and 64 CAM entries for writes; latency as low as 8 clock cycles
• UVM testbench with embedded assertions and options to incorporate a DDR5/4 PHY into a verification environment

Deliverables

• Executable .run installation file which includes: – Custom-configured RTL source code (using Synopsys’ coreConsultant or coreAssembler tool) – Synthesis, design-for-test, and power reduction scripts – SystemVerilog UVM verification environment containing sample integrations of the DDR5/4 Controller with the DesignWare DDR5/4 PHY and sample test cases – Performance evaluation test case to enable the user to evaluate performance using their own traffic patterns
• Databook (PDF)
• Release notes (PDF)
• coreConsultant/coreAssembler tools to generate RTL
• Optional add-on Synopsys Platform Architect

Applications

• Enterprise servers and data centers
• Storage & networking
• High-performance computing
• AI and machine learning
• Digital office

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