PCIe 5.0 IP in Samsung 7nm
Using leading-edge design, analysis, simulation, and measurement techniques, Synopsys delivers exceptional signal integrity and jitter performance that exceeds the PCI Express standard’s electrical specifications. The high-margin, robust PHY architecture tolerates process, voltage and temperature (PVT) manufacturing variations and is implemented with standard CMOS digital process technologies.
The multi-tap transmitter and receiver equalizers, along with the advanced built-in diagnostics and ATE test vectors, enable customers to control, monitor and test for signal integrity without the need for expensive test equipment. This provides on-chip visibility into actual link and channel performance to quickly improve signal integrity, reducing both product development cycles and the need for costly field support.
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Video Demo of the PCIe 5.0 IP in Samsung 7nm
This video features Synopsys’ DesignWare PHY IP for PCI Express 5.0 meeting the Rev. 1.0 specification’s channel performance and jitter tolerance. The IP operates at 32GT/s data rate and exceeds the required 36 dB channel loss to enable high-throughput over the toughest, long-reach channels. Accelerate your move to PCI Express 5.0 with Synopsys’ DesignWare IP.
PCI Express PHY IP
- PHY/PCS Logical Sub-Block IP Core for PCIe supporting PCIe 5.0, 4.0, 3.1 PHY/PMA and compliant to the PIPE 5.2 and 4.4.1 Specifications
- PCIe 2.1 Controller with the PHY Interface for PCI Express (PIPE) specification and native user interface support
- PCIe 3.0, 2.1, 1.1 Controller with the PHY Interface for PCI Express (PIPE) specification and native user interface support
- PCIe 5.0 PHY in TSMC (16nm)
- PCIe 2.1 Controller supporting Root Port, Endpoint, Dual-mode Configurations, with Built-in DMA and Configurable AMBA AXI Interconnect
- PCIe4 Ethernet SERDES PHY - TSMC N5