The PMCC_OBUF12G is a differential CML 50Ω terminated
output driver for datarates from DC up to 12Gb/s. The buffer can
also be used for up to 8GHz clock driving. Depending on input
signal level it can work in two modes. If the input signal level is
lower than 0.1V p-p, the PMCC_OBUF12G will work as a linear
amplifier. When input signal level is higher than 0.1V p-p diff.,
this macro-block works as a limiting amplifier with 500mV
single ended or 1V differential output swing. The buffer features
output pattern depended jitter below 0.5ps. For power saving, the
buffer has a reduced swing mode (600mV p-p differential).
Three bit control is provided for biasing current adjustment
within ±20% to optimize PMCC_OBUF12G performance for the
- Data-rates up to 12GHz.
- Power consumption 40mW
- Differential or single ended 50Ω terminated output.
- Deterministic jitter below 0.5ps
- S22 below – 7.5dB @ f<10GHz
- Normal and low swing output
- Stand-by mode
- Extra low power at upto 12Gb/s. Can serve as LVDS buffer.
- GDS II file
- Netlist for Spectre simulation
- Layout and Schematic (DRC & LVS) verification reports
- Complete macro datasheet
- Macro integration/application notes
- Design kit and software related information
- Optional deliverables are:
- Library containing entire hierarchy of macro schematic and layout cells
- Extracted views containing parasitic components from layout
- Verilog-A model replicating macro functionally
- Simulation test-benches
- Optional components specific to macro: biasing, specialized I/Os, glue-logic, transmission lines etc.