Digital Rotation (DR) signals a revolution in image rotation and de-rotation. It removes the need for cumbersome mechanical rotation hardware, superseding it with state-of-the-art digital image processing. Many of DR’s features can be configured while the system is still running, keeping the user fully in control. DR works seamlessly with the rest of the system, providing native camera interfaces on both the input and output, and can even compensate for frame errors. Reliable, maintenance-free and targeted to low-cost FPGA devices, DR is a rotation solution designed for the digital age.
- The full DR core offers:
- A degree of rotation that can be specified to within a granularity finer than 0.36°.
- Three dynamically selectable HD video input streams.
- Output can be configured to either SD or HD at build-time.
- Pixel interpolation mode can be switched during operation between nearest neighbour or bilinear interpolation.
- Camera link format inputs.
- SDI output.
- Dedicated memory controller and cache optimised for interfacing with DDR3 SDRAM.
- Rotation can be bypassed when required.
- Support for both interlaced and non-interlaced video formats.
- Detects incorrect timing in the incoming video signal and attempts to resynchronise.
- A cut-down variant can offer a subset of these features, including:
- Dynamically selectable rotation of a single input stream in steps of 90°.
- Considerable savings on FPGA resource usage over the full DR core.
- DR’s rich feature set provides a complete replacement for mechanical rotation, with more besides:
- An angle of rotation dynamically selectable in sub-degree steps.
- Three HD input streams between which the user can switch during operation.
- Two run-time selectable pixel interpolation modes.
- Video output factory-configurable to HD (1920×1080) or SD (720×576).
- Native camera interfaces on both the input and the output.
- Efficient, flexible memory-interfacing optimised for low-cost dynamic memory.
- Designed for integration as part of a customer’s FPGA system.
- For situations where FPGA resource usage is a challenge, a 90°-step variant with fewer features can be provided, achieving economies on silicon usage.
Block Diagram of the Digital Rotation