The VLVm1 is the first of GPT’s optimized Variable Length Vector (VLV) DSP IP cores targeted at image processing. VLVs allow forward and backward code compatibility by architecturally specifying a vector length. Unlike SIMD which has a fixed width, VLV specifies an arbitrary and dynamic length for vectors. An implementation can be customized for performance/power/price based on the number of vector elements to be executed simultaneously. Code does not need to be recompiled when the vector length changes. Non-power-of-two vectors can be easily specified.
Combining GPT’s superscalar out-of-order ‘Great Wall’ CPU with a VLV execution unit, the VLVm1 processors run at up to 3GHz.
- Vector length register to specify any length (up to 64KB)
- Out-of-order instruction and out-of-order element processing
- Integer 16/32-bit, floating point 16-bit
- General computing and image processing vector instructions
- Software forward and backward compatibility