The Digital Stabilisation IP Core fully supports Xilinx Zynq capabilities of cross domain FPGA-ARM-processing. This enables the Core to leverage the power of software based adaptive algorithms without impacting the throughput performance of highly pipelined FPGA processing. The DS Digital Stabilisation IP Core is designed to meet the most demanding requirements of military driver assistance systems. Nevertheless it can be easily tailored to different applications using the comprehensive range of run-time control parameters.
- Up to 150 fps, up to 1080p, depending on target device and resources
- Latency of less than 1 frame (core only)
- Stabilisation for daylight, IR, and fused video streams.
- Stabilisation accuracy performance of the total frame-to-frame movement is equivalent to ±1% of the vertical field of view (VFOV) of the camera.
- Stabilisation for camera movements in x and y directions (translation) and rolling (either centred within or outside of the image frame).
- Recovery from irregular, single, movements of ± 15% of the VFOV within 0.1 seconds of the event.
- Full, run-time parametric control of local and global scene movement response characteristics.
- Translation and rotation stabilisation
- Movement accuracy better than 1% frame-to-frame error
- Panning filter control
- Real-time, low-latency
- Up to 150 fps
- Up to 1080p
- Full Xilinx Zynq support
Block Diagram of the Digital Stabilisation IP Core