Digital Video Broadcasting (DVB) is a suite of open standards for digital television. The interface schemes for DVB are defined in the European standard EN 50083-9, “Interfaces for CATV/SMATV Headends and Similar ProfessionalEquipment”. DVB via Asynchronous Serial Interface (DVB-ASI) is one of the primary mechanisms to transport MPEG-2 based streams over cable media.
DVB-ASI is a three-layered architecture with the top layer (Layer 2) specified by IEC 13818-1 and the bottom layers, Layer 1 and Layer 0, specified by the Fibre Channel standard IEC 141165-1, part 1. This IP core along with LatticeECP3™ SERDES/PCS implements Layer 1 of the DVB-ASI interface. A part of Layer 2 functionality is also supported by the IP core.
- Configurable Tx FIFO supporting independent Layer 2 transmit clock
- Configurable Rx FIFO supporting independent Layer 2 receive clock
- Automatic start of packet comma insertion in the transmit side
- Rate-matching comma insertion in the transmit side
- Handshake signals for sync and data valid for transmitter and receiver
- Tx and Rx FIFO full indicators
- Rx sync byte indicator for identifying start-of-packet
- Optional configurable almost full and almost empty indicators for the FIFOs
- Matching port names for seamless connection with LatticeECP3 SERDES/PCS
- Layer 2 functions including lock, sync byte, packet size, runt and giant indicators
Block Diagram of the Digital Video Broadcasting - (DVB-ASI) IP Core