The Discrete Fourier Transform (DFT) core is a fundamental building block for implementing the SC-FDMA uplink transmission scheme selected for 3rd Generation Partnership Project (3GPP) Long Term Evolution (LTE) wireless systems. The DFT core is designed to meet the transform point size requirements for 3GPP LTE systems. The DFT core provides highly optimized implementation along with system level fixed point C-models, and further reduces implementation time for 3GPP LTE systems.
- A fixed point bit-accurate C-Model to enable system level analysis of Xilinx DFT core.
- Transform sizes from 12 to 1200 points with the option to change size frame by frame.
- Less than 26 μs total latency when transforming 1200 points at 245.76 MHz (using any combination of sizes)
- Up to 18-bit two’s complement input data width, up to 18-bit two’s complement output data width with 4-bit block exponent.
- Direct and inverse DFT supported on frame-by frame basis.
- Addition of 1296 point size as required by the 3GPP LTE specification
- Optional support of 1536 point size required for 15 MHz bandwidth 3GPP LTE systems
- Option to tradeoff between area resources or speed performance