The Digital Blocks DB9000AXI LCD / OLED Display Controller IP Core interfaces a microprocessor and frame buffer memory via the AMBA AXI Protocol Interconnect to a LCD or OLED display panel.
The Display Controller Verilog RTL IP Core comes in releases supporting baseline display processing features and releases with advanced display processing, such as Multi-layer Overlay Windows with optional Alpha Blending, Scaling, Color Space Conversion, 4:2:2 YCrCb with Re-sampling & conversion to RGB, and Hardware Cursor and Frame Buffer Compression. Optional features provide the customer with targeted features while saving on VLSI resources and licensing costs.
The DB9000AXI contains a selectable 256 / 128 / 64 / 32-bit AXI Master Interface with the higher data widths targeting higher resolution, higher color depth LCD or OLED display panels, with their resulting high frame buffer memory data bandwidth requirements.
The DB9000AXI IP Core can be implemented in an ASIC, ASSP, or FPGA device with an embedded microprocessor, an AMBA AXI Interconnect fabric, and SDRAM Controller for access to frame buffer memory. Typically, the microprocessor is an ARC, ARM, Intel, MIPS, OpenSPARC, PowerPC, RISC-V, or Tensilica processor and frame buffer memory is off-chip DDR 1-5 SDRAM.
- Wide range of programmable Display Panel resolutions:
- From Quarter VGA up to 1920x1080 HD, 4K, and 8K
- Releases supporting baseline display requirements and releases with following optional display processing features:
- Overlay Windows with additional options:
- Alpha Blending
- Color Space Conversion (CSC)
- 4:2:2 YCrCb with Re-sampling & CSC to RGB
- Programmable size, placement, & format
- Hardware Cursor
- Frame Buffer Compression
- Optional features provide customer with the exact features needed while saving on VLSI resources and licensing costs.
- Color Palette RAM per layer or single Palette for integrated display image
- Interface to parallel RGB, LVDS, HDMI, DisplayPort, MIPI, Vby1, BT.656
- Programmable 1,2,4,8 Port Display Panel interfaces
- Programmable horizontal & vertical timing parameters:
- front porch, back porch, sync width, pixels-per-line, lines-per-panel
- horizontal & vertical sync polarity
- Programmable frame buffer bits-per-pixel (bpp) color depths:
- 1, 2, 4, 8 bpp mapped through Color Palette
- 16, 18, 24 bpp non- Palette
- AMBA AXI / AHB / APB Interconnect:
- Selectable 256 / 128 / 64 / 32-bit AXI Master Port for DB9000AXI DMA access of frame buffer memory for driving the display
- Selectable 256 / 128 / 64 / 32-bit AXI (or AHB / APB) Slave Port for control & status interface to microprocessor
- Power up and down sequencing support
- 9 sources of internal interrupts with masking control
- Little-endian, big-endian, or Windows CE mode
- Linux OS driver
- Fully-synchronous, synthesizable Verilog RTL core, with rising-edge clocking, No gated clocks, and No internal tri-states
- Verilog RTL Source or technology-specific netlist.
- Comprehensive testbench suite with expected results.
- Synthesis scripts.
- Installation & Implementation Guide.
- Technical Reference Manual.
- Linux OS Driver