English
You are here:
Display Port 1.2 Tx PHY & Controller IP (Silicon Proven in STMicro 28FDSOI)
Our Display Port is VESA DP1.1a, DP1.2 and eDP compliant with four main lanes and an auxiliary channel The DP transmitter acceptsDP1.1a HBR (2.7Gbps) and RBR (1.62Gbps) data rates; it can also support turbo mode (3.24Gbps) and HBRII (5.4Gbps) of DP1.2 standard. Signals are sampled from 1/2/4-lane double-wide DP stream data.
View Display Port 1.2 Tx PHY & Controller IP (Silicon Proven in STMicro 28FDSOI) full description to...
- see the entire Display Port 1.2 Tx PHY & Controller IP (Silicon Proven in STMicro 28FDSOI) datasheet
- get in contact with Display Port 1.2 Tx PHY & Controller IP (Silicon Proven in STMicro 28FDSOI) Supplier
Block Diagram of the Display Port 1.2 Tx PHY & Controller IP (Silicon Proven in STMicro 28FDSOI)
Display Port V1.2 Tx PHY IP IP
- Display Port 1.4 Tx PHY & Controller IP (Silicon Proven in TSMC 28HPC+)
- Display Port 1.4 Tx PHY & Controller IP (Silicon Proven in UMC 28HPC+)
- Display Port 1.4 Tx PHY & Controller IP (Silicon Proven in UMC 40LP)
- Display Port 1.4 Tx PHY & Controller IP (Silicon Proven in TSMC 40LP)
- Display port 1.4 Tx PHY & Controller IP, Silicon Proven in TSMC 12FFC