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Display Port 1.4 Tx PHY & Controller IP (Silicon Proven in UMC 40LP)
DisplayPort version 1.4 compliant transmitter PHY supports 1.62Gbps (RBR) to 5.4Gbps (HBR2) bit rate Integrated 100-ohm termination resistors with common-mode biasing Integrated equalizer with tunable strength Configurable analog characteristics CDR bandwidth, Equalizer strength, Terminator resistance, BGR voltage, Regulator voltage, Support PLL test and internal analog signal monitor
• 1.8V/0.9V power supply
• 1.8V/0.9V power supply
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Block Diagram of the Display Port 1.4 Tx PHY & Controller IP (Silicon Proven in UMC 40LP)
Display Port Tx IP in UMC 28nm IP
- Display Port 1.4 Tx PHY & Controller IP (Silicon Proven in UMC 28HPC+)
- Display Port 1.2 Tx PHY & Controller IP (Silicon Proven in STMicro 28FDSOI)
- Display Port 1.4 Rx PHY & Controller IP (Silicon Proven in UMC 28HPC+)
- Display Port 1.4 Rx PHY & Controller IP (Silicon Proven in UMC 40LP)
- Display Port 1.4 Rx PHY & Controller IP (Silicon Proven in TSMC 40LP)
- Display Port 1.4 Rx PHY & Controller IP (Silicon Proven in IDM 180nm /150nm)