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Display Port v1.4 Tx PHY & Controller IP, Silicon Proven in TSMC 12FFC
DisplayPort version 1.4 compliant transmitter PHY supports 1.62Gbps (RBR) to 5.4Gbps (HBR2) bit rate Integrated 100-ohm termination resistors with common-mode biasing Integrated equalizer with tunable strength Configurable analog characteristics CDR bandwidth, Equalizer strength, Terminator resistance, BGR voltage, Regulator voltage, Support PLL test and internal analog signal monitor 1.8V/0.9V power supply.
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Block Diagram of the Display Port v1.4 Tx PHY & Controller IP, Silicon Proven in TSMC 12FFC
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