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ARC VPX5 high-performance, 512-bit VLIW / SIMD DSP IP for high-end computation applications
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Display Stream Compression (DSC 1.2) Encoder
The Trilinear Technologies Display Stream Compression (DSC) Encoder offers real-time compression of high-definition streams with resolutions up to 8K. The core supports 8, 10, 12, 14 or 16 bits per pixel input using either RGB or YCbCr in 4:4:4 or 4:2:2 format. The DSC Encoder core integrates industry standard interfaces for host configuration and control, video input, and output.
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Block Diagram of the Display Stream Compression (DSC 1.2) Encoder IP Core
VESA DSC IP
- VESA DSC (Display Stream Compression) 1.2a Video Encoder
- VESA DSC (Display Stream Compression) 1.2a Video Decoder
- VESA DSC Encoder
- VESA Display Stream Compression (DSC) IP Core
- MIPI DSI-2 controllers with VESA DSC for high-speed serial interface between application processor and displays
- VESA DSC Encoder IP