Display Stream Compression (DSC 1.2) Encoder

The Trilinear Technologies M27 DSC 1.2 Encoder offers real time compression of high definition streams with resoltions up to 8K. The Display Stream Compression (DSC) standard from the Video Electronics Standards Assocaiton (VESA) offers visually lossless compression for high definition applications. The M27 Encoder core is fully compliant with the VESA DSC 1.2 standard and is available for both FPGA and ASIC implementations.

The M27 Encoder core is delivered with an industry standard AMBA 3.0 Peripheral Bus interface for host configuration and control. Input video is provided to the encoder using an industry standard parallel data format with line and frame indicator signals. The output interface is AXI4-Stream Protocol compliant. The Encoder core supports 8, 10 or 12 bits per pixel using either the RGB or YCbCr in 4:4:4 or 4:2:2 format.

The M27 DSC Encoder core is delivered with a complete ‘C’ reference driver and a fully documented software API. The core is available on the Trilinear Technologies’ Cobra Development platform based on the Xilinx KC705. This FPGA based reference system provides a complete development environment for core evaluation as well as early software development.