Tunable SM4 (ECB, CBC, CTR, XTS, CCM, GCM) accelerator - optional SCA protection
Display Stream Compression (DSC 1.2) Encoder
The M27 Encoder core is delivered with an industry standard AMBA 3.0 Peripheral Bus interface for host configuration and control. Input video is provided to the encoder using an industry standard parallel data format with line and frame indicator signals. The output interface is AXI4-Stream Protocol compliant. The Encoder core supports 8, 10 or 12 bits per pixel using either the RGB or YCbCr in 4:4:4 or 4:2:2 format.
The M27 DSC Encoder core is delivered with a complete ‘C’ reference driver and a fully documented software API. The core is available on the Trilinear Technologies’ Cobra Development platform based on the Xilinx KC705. This FPGA based reference system provides a complete development environment for core evaluation as well as early software development.
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Block Diagram of the Display Stream Compression (DSC 1.2) Encoder IP Core

VESA DSC IP
- VESA DSC Encoder
- VESA Display Stream Compression (DSC) IP Core
- VESA DSC (Display Stream Compression) 1.2a Video Encoder
- VESA DSC (Display Stream Compression) 1.2a Video Decoder
- MIPI DSI-2 controllers with VESA DSC for high-speed serial interface between application processor and displays
- VESA DSC Decoder IP