DisplayPort 1.4a IP Core
The Bitec DisplayPort IP core for FPGA and ASIC devices offers a cost-efficient industry leading solution to rapidly develop and deliver displays offering a superior viewing experience within ever-shrinking product lifecycles. The core is used extensively in FPGA based products and in high-volume OEM ASIC applications.
The Bitec DP IP core accepts 1,2,3 or 4 lanes at arbitrary link rates. In accordance with the DP specification 1.4a, the core will adapt and train to the transmitting source capability via a firmware driven policy maker API.
The source and sink cores accept v/h/d-sync and parallel RGB data. Audio data and raw Auxiliary data ports to the cores provide flexible side-band messaging.
Bitec also offer a tailoring service for bespoke designs. For more information contact Bitec.
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