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DisplayPort Transmitter & Receiver
Logic Fruit Technologies has designed & implemented DISPLAY PORT Transmitter & Receiver IP Cores supporting multiple line rates up to 8.1Gbps. The IP cores have been developed as per Display Port specifications DP2.0/eDP1.5.
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Block Diagram of the DisplayPort Transmitter & Receiver IP Core
DISPLAY PORT IP
- PCI Express GEN-3/Display Port SERDES PHY - Samsung 28 28LPP
- Display Port 1.2 Tx PHY & Controller IP (Silicon Proven in STMicro 28FDSOI)
- Display Port 1.4 Rx PHY & Controller IP (Silicon Proven in UMC 28HPC+)
- Display Port 1.4 Tx PHY & Controller IP (Silicon Proven in TSMC 28HPC+)
- FPD LVDS Display Interface - 1 & 2 Port LVDS Panels
- Display Port Transmitter IP