English
You are here:
DisplayPort Tx PHY & Controller
The INNO eDP TX PHY is VESA DP1.1a, eDP v1.3 compliant and can be configured to support from 1 to 4 lanes. By providing up to HBR output at 2.7Gb/s, the INNO eDP TX PHY can carry high quality multi-channel audio data along with all standard and high-definition consumer electronics video formats. Composed of both PHY and controller, the INNO eDP TX offers simple SOC implementation.
Features
- <0.62mm^2 for PHY in SMIC28nm
- eDP v1.3 compliant Tx PHY
- Data rate from 1.62Gbps/2.7Gbps per lane
- Available in 1-4 lane configurations
- 20-bit, 8b/10b encoded, per lane input
- Alternatively output the link rate clock or half of the link rate clock with or without SSC modulation
- Supports transceiver for AUX channel working in 1MHz Manchester II coding mode
- Programmable output voltage swing and pre-emphasis
- APB slave interface available for accessing internal analog registers
- Multiphase 4MHz fixed bandwidth PLL with low jitter
- Lower power operation with power management features
- Embedded ESD, scan support logic for full BIST logic
Deliverables
- Databook and detailed physical implementation guides
- Complete set of timing models
- Library Exchange Format (LEF)
- Encrypted Verilog Models
- Layout vs. Schematic (LVS) report
- GDSII database for foundry merge
Applications
- Set top boxes
- HD DVD
- PS3
- A/V devices
- PC
- Video Camera
View DisplayPort Tx PHY & Controller full description to...
- see the entire DisplayPort Tx PHY & Controller datasheet
- get in contact with DisplayPort Tx PHY & Controller Supplier
4Lanes
- MIPI D-PHY 1.5Gbps (4-lanes TX/RX, PLL Integrated) TSMC 28HPM
- MIPI D-PHY 2.0Gbps (4-lanes TX/RX, PLL integrated) TSMC 16FF+LL
- MIPI D-PHY 2.0Gbps (4-lanes RX) TSMC 16FF+LL
- MIPI D-PHY 2.0Gbps (4-lanes TX, PLL integrated) TSMC 16FF+LL
- MIPI D-PHY 1.5Gbps (4-lanes RX) GF 55LPe
- MIPI D-PHY 1.5Gbps (4-lanes TX, PLL Integrated) GF 55LPe