DisplayPort Video Interface (up to 5.4Gbps)
The Altera® DisplayPort MegaCore® function implements a receiver and transmitter at raw bit rate of 1.62, 2.7, or 5.4 Gbps per lane with support to have 1, 2, or 4 differential data pairs (lanes) in a Main Link. Data is 8b/10b encoded where each 8 bits of information is encoded with a 10 bit symbol. So the effective data rates after decoding are 1.296, 2.16, and 4.32 Gbps per lane (or 80% of the total) and support DisplayPort v1.2 specification.
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DisplayPort IP
- HDCP 2.3 Embedded Security Modules on DisplayPort/USB Type-C
- VESA DisplayPort 1.4 Forward Error Correction (FEC) Receiver
- VESA DisplayPort 1.4 Forward Error Correction (FEC) Transmitter
- VESA DisplayPort 1.4 RX IP Subsystem for Xilinx FPGAs
- VESA DisplayPort 2.0 FEC RX
- Display Port v1.4 Tx PHY & Controller IP, Silicon Proven in TSMC 12FFC