The Divider Generator LogiCORE™ IP provides a resource efficient and high performance solution for integer division. The integer division can be implemented using Radix-2 non-restoring division, or High Radix division with prescaling division algorithms.
The Radix-2 algorithm is implemented using the logic fabric and provides up to 32 bits operands along with the ability to control the degree of parallelism used in the algorithm. By controlling the parallelism of the implementation, users can make trade-offs between performance and resources. The High-Radix division with prescaling algorithm is designed to exploit the DSP48 (multiply-add) capability to provide an efficient, low-latency implementation for up to 54 bits operands. The Radix-2 algorithm is suitable for implementing smaller operand division, and High Radix division, better suited for implementing large (above about 25 bits wide) operands.
- AXI4-Stream-compliant interfaces
- Integer division with operands of up to 64 bits wide
- Offers Radix-2, LUTMult and High Radix implementation algorithms to allow choice of resource and latency trade-offs
- Optional operand widths, synchronous controls, and selectable latency
- Optional divide by zero detection
- C model for system-level simulation (bit accurate with core except for division by zero)