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Scalable multicore architecture for a range of macrocells, small cells, cloud-RAN, DFE/DPD/ and more
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DMA for PCI Express (PCIe) Subsystem
The Xilinx® LogiCORE™ DMA for PCI Express® (PCIe) implements a high performance, configurable Scatter Gather DMA for use with the PCI Express Integrated Block. The IP provides an optional AXI4-MM or AXI4-Stream user interface.
Features
- DMA for PCI Express Subsystem connects to the PCI Express Integrated Block. Both IPs are required to build the PCI Express DMA solution
- Support for 64, 128, 256, 512-bit datapath for UltraScale+™, UltraScale™ devices. Support for 64 and 128-bit datapath for Virtex®-7 XT devices
- Up to 4 host-to-card (H2C/Read) data channels for UltraScale+, UltraScale devices. Up to 2 such channels for Virtex-7 XT devices
- Up to 4 card-to-host (C2H/Write) data channels for UltraScale+, UltraScale devices. Up to 2 such channels for Virtex-7 XT devices
- 64-bit source, destination, and descriptor addresses
- Per channel descriptor bypass for custom descriptor creation
- Configurable user interface
- Common AXI4 memory mapped (MM) user interface
- A separate AXI4-Stream user interface
- AXI Master interfaces enable PCIe reads and writes to bypass the DMA engine
View DMA for PCI Express (PCIe) Subsystem full description to...
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Interface and Interconnect
- FlexNoC Network on Chip SoC Interconnect IP
- Cache Coherent Interconnect
- AXI- Interconnect : Advanced Extensible Interface Bus IP
- Configurable PCI Express 4.0 Controller for ASIC/SoC with a configurable AMBA AXI3/AXI4 user interface
- Serial Peripheral Interconnect Master & Slave Interface Controller
- Physical Layer Interface Core