Provides a general purpose input/output interface to the AXI4-Lite interface. Only needed for Zynq if you exceed the 54 GPIO built in.
- Supports the AXI4-Lite interface specification
- Supports configurable single or dual GPIO channel (s)
- Supports configurable channel width for GPIO pins from 1 to 32 bits
- Supports dynamic programming of each GPIO bit as input or output
- Supports individual configuration of each channel
- Supports independent reset values for each bit of all registers
- Supports optional interrupt request generation
- Mature source IP has been re-engineered for full DAL-A compliance for airworthiness and design assurance for safety-critical programs, supporting and simplifying the compliance effort at the FPGA level.
- Encrypted source along with a complete certification data package (CDP) including all artifacts required for chip-level compliance.