Provides a 32-bit free-running timebase and watchdog timer.
- Connects as a 32-bit slave on a AXI4-Lite Interface
- Watchdog timer (WDT) with selectable timeout period and interrupt
- Configurable WDT enable: enable-once or enable disable
- One 32-bit free-running timebase counter with rollover interrupt-Dual control register
- Mature source IP has been re-engineered for full DAL-A compliance for airworthiness and design assurance for safety-critical programs, supporting and simplifying the compliance effort at the FPGA level.
- Encrypted source along with a complete certification data package (CDP) including all artifacts required for chip-level compliance.