DO-254 Block Memory Generator 1.00a

Features

• Choice of Native Interface, AXI, or AXI4-Lite
• Example Design helps you get up and running quickly
• Native interface core
• Generates Single-Port RAM, Simple Dual-Port RAM, True Dual-Port RAM, Single-Port ROM, or Dual-Port ROM
• Performance up to 450 MHz
• Data widths from 1 to 4096 bits
• Memory depths from 2 to 128k
• Variable Read-to-Write aspect ratios in Virtex®-7, Kintex®-7, Virtex-6, Virtex-5 and Virtex-4 FPGAs
• Option to optimize for resource or power
• Ability to initialize the memories with pre-defined values
• Supports individual write enable per byte in Virtex-7, Kintex-7, Virtex-6, Virtex-5, Virtex-4, Spartan®-6 and Spartan- 3A / XA DSP with or without parity
• Selectable per-port operating mode: WRITE_FIRST, READ_FIRST or NO_CHANGE
• Support for hard and soft Error Correction (ECC) feature
• AXI interface core
• Generates Dual Port RAM
• Performance up to 300 MHz
• Data widths ranging from 8 to 64 bits
• Common features in Native interface and AXI cores
• Variable port aspect rations for dual-port configurations
• VHDL and Verilog behavioral models optimized for fast simulation times
• Structural simulation model option for precise simulation

Benefits

• Mature source IP has been re-engineered for full DAL-A compliance for airworthiness and design assurance for safety-critical programs, supporting and simplifying the compliance effort at the FPGA level.

Deliverables

• Encrypted source along with a complete certification data package (CDP) including all artifacts required for chip-level compliance.

• see the entire DO-254 Block Memory Generator 1.00a datasheet
• get in contact with DO-254 Block Memory Generator 1.00a Supplier