A dedicated embedded block multi-port memory controller that greatly simplifies the task of interfacing Spartan-6 devices to the most popular memory standards. Note: Spartan-6 equivalent of the 7-Series DDRx IP
- DDR, DDR2, DDR3, and LPDDR (Mobile DDR) memory standards support
- Up to 800 Mb/s (400 MHz double data rate) performance
- Up to four MCB cores in a single Spartan-6 device
- Configurable dedicated multi-port user interface to FPGA logic
- Memory Bank Management
- Embedded controller and physical interface (PHY)
- Predefined pinouts (I/O locations) for each MCB
- Common memory device options and attributes support
- Automatic delay calibration of memory strobe and read data inputs
- Optional automatic calibration of FPGA on-chip input termination for optimal signal integrity
- Supported by Xilinx® CORE Generator and Embedded Development Kit (EDK) design tools
- Mature source IP has been re-engineered for full DAL-A compliance for airworthiness and design assurance for safety-critical programs, supporting and simplifying the compliance effort at the FPGA level.
- Encrypted source along with a complete certification data package (CDP) including all artifacts required for chip-level compliance.