Provides the control interface for external synchronous, asynchronous SRAM, Flash and PSRAM/Cellular RAM memory devices through the AXI interface, designed to interface with the AXI4 interface.
- Supports AXI4 specification for AXI interface
- Full AXI4 slave interface supports 32-bit address bus and 32/64-bit data bus
- Supports 32-bit configurable AXI4-Lite control interface to access internal registers
- Supports Burst transfers of 1-256 beats for INCR burst type and 2, 4, 8, 16 beats for WRAP burst type
- Supports AXI narrow transfers, unaligned transfer type of transactions
- Supports multiple (up to 4) external memory banks
- Supports independent memory configuration of each memory bank
- Supports memory data widths of 64-bit, 32-bit, 16-bit and 8-bit for each of the memory banks
- Mature source IP has been re-engineered for full DAL-A compliance for airworthiness and design assurance for safety-critical programs, supporting and simplifying the compliance effort at the FPGA level.
- Encrypted source along with a complete certification data package (CDP) including all artifacts required for chip-level compliance.