Generates fully verified first-in, first-out (FIFO) memory queues ideal for applications requiring in-order data storage and retrieval. Basically it puts logic around a BRAM to make it a FIFO. Note: Requires Block Memory Generator as sub-IP.
- FIFO depths up to 4,194,304 words
- FIFO data widths from 1 to 1024 bits for Native FIFO configurations and up to 4096 bits for AXI FIFO configurations
- Non-symmetric aspect ratios (read-to-write port ratios ranging from 1:8 to 8:1)
- Supports Independent or common clock domains
- Selectable memory type (Block RAM, Distributed RAM, Shift Register, or Built-in FIFO)
- Native or AXI interface (AXI4, AXI4-Lite, or AXI4-Stream)
- Synchronous or asynchronous reset option
- Supports Packet Mode
- Supports Error Correction (ECC) and Injection feature for certain configurations
- Supports First-Word Fall-Through (FWFT)
- Supports Embedded Register option for Block RAM and Built-in FIFO primitive based implementations
- Supports ? Empty/Full, Almost Empty/Full, and Programmable Empty/Full signals
- Mature source IP has been re-engineered for full DAL-A compliance for airworthiness and design assurance for safety-critical programs, supporting and simplifying the compliance effort at the FPGA level.
- Encrypted source along with a complete certification data package (CDP) including all artifacts required for chip-level compliance.