The interface between the LMB and the BRAM block peripheral. A BRAM memory subsystem consists of the controller along with the actual BRAM components that are included in the BRAM block peripheral. Almost certainly needed for any MB system.
- LMB v1.0 bus interfaces with byte enable support
- Used in conjunction with BRAM block peripheral to provide fast BRAM memory solution for MicroBlaze ILMB and DLMB ports
- Supports byte, half-word, and word transfers
- Mature source IP has been re-engineered for full DAL-A compliance for airworthiness and design assurance for safety-critical programs, supporting and simplifying the compliance effort at the FPGA level.
- Encrypted source along with a complete certification data package (CDP) including all artifacts required for chip-level compliance.