Process Detector (For DVFS and monitoring process variation), TSMC 12FFC
DPA- and FIA-resistant Ultra Low Power FortiCrypt AES IP core
This can be an ideal solution for battery-powered devices, which often work in a power-save mode and wake up from time to time for as-short-as-possible periods.
In addition, devices that do massive AES decrypt/encrypt operations can benefit from this IP core, by saving on electricity bills.
This is a unique solution in the market since it consumes significantly less power than other commercially available solutions.
The AES ULP-DPA-FIA IP Core, as well as all the FortiCrypt products, is based on RAMBAM - the next-generation purely algorithmic, implementation-agnostic protection scheme of AES. It is designed to provide the highest level of protection against side-channel attacks (SCA) and fault injection attacks (FIA) including SIFA.
The RAMBAM protection scheme utilizes masking methods based on finite field arithmetic that implement attack resistance without incurring extra latency costs.
The core protection mechanism was verified using the rigorous Test Vector Leakage Assessment (TVLA) test at 1B traces, both by FortifyIQ and by a third-party Common Criteria lab. Resistance to attacks was validated analytically and on a physical device. The cores are fully synthesizable and do not require custom cells or special place & route handling.
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Block Diagram of the DPA- and FIA-resistant Ultra Low Power FortiCrypt AES IP core
side channel IP
- Tunable Cryptography
- Active Shield - Active mesh against tampering attacks - PQC Ready
- Tunable AES (ECB, CBC, CTR, XTS, CCM, GCM) accelerator - optional SCA protection
- High-performance AES-GCM accelerator - optional SCA protection
- High-performance AES-XTS accelerator - optional SCA protection
- Tunable DES - Triple DES (ECB, CBC, CTR) accelerator - optional SCA protection