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Super-Fast 8051 Microcontroller Core with Configurable Features and Peripherals
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DPA Resistant AES Core
As one of the most widely used encryption algorithm for both commercial and government applications, the DPA Resistant offerings include both AES-128 and AES-256 cryptographic cores. These cores are validated to resist first– and second– order DPA attacks up to 10 million traces and can be optimized for size, speed and security level .
The DPA Resistant AES Core is a high-security AES primitive that offers chipmakers an easy-to-integrate security solution with built-in side-channel resistance for cryptographic functions across a wide range of connected devices. In addition, there is also a software version of the solution, available as DPA Resistant AES Software Library.
The DPA Resistant AES Core is a high-security AES primitive that offers chipmakers an easy-to-integrate security solution with built-in side-channel resistance for cryptographic functions across a wide range of connected devices. In addition, there is also a software version of the solution, available as DPA Resistant AES Software Library.
Features
- Core implements a very high-security AES primitive
- Available as AES-128 and AES-256 encrypt and decrypt
- Simple control/status interface
- Implements DPA countermeasures such as LMDPL (LUT-Masked Dual-rail with Pre-charge Logic) gate-level masking and other schemes
- No routing constraints necessary for LMDPL gate-level masking
- Design Priorities:
- Security
- Performance
- Area
Benefits
- High-performance and DPA resistance-proven AES cryptographic core
- Provides a higher level of protection than standard AES cores
- Extensively validated against side-channel attacks
- Highly flexible for integration with standard cipher modes such as CBC, ECB, etc.
- Easy-to-integrate into SoCs
Deliverables
- The DPA Resistant AES solution is available as either an IP core or a software library.
- DPA Resistant AES Core:
- Verilog RTL reference design
- Synthesis Inputs
- SDC constraint file suitable for FPGA or ASIC synthesis
- Documentation
- Usage guide
- Functional Testbench
- NIST-compliant test vectors
- Development and Test Environment (optional)
- DPA Workstation
- Implementation on reference FPGA board
- Integrated testing framework
- DPA Resistant AES Software Library:
- Reference design source code with build scripts and test vectors for the reference (ARM-based) platform
- Packaged libraries for a specific platform
- Development and Test Environment (optional)
- Hardware reference board for a specific platform
- DPA Workstation
- Specification sheet for DPA-resistant target level on a specific platform
- Documentation for library usage
- Cryptography Research software services
- Analysis, development, integration, optimization, and support
- Cryptography Research software support
- Quarterly or semiannual bug fixes and enhancements
- Periodic upgrades depending on customer priority
- Optional Cryptography Research services
- DPA and DPAWS training
- Software testing: testing performed either by Cryptography Research or by customer after training from Cryptography Research
Applications
- Aerospace and Defense
- Content Protection
- Mobile
- Storage
- Secure Communications
- Automotive
- Payments/Point-of-Sale
- Internet of Things
Block Diagram of the DPA Resistant AES Core IP Core
View DPA Resistant AES Core full description to...
- see the entire DPA Resistant AES Core datasheet
- get in contact with DPA Resistant AES Core Supplier
AES
- UFS 3.0 Host Controller with AES Encryption compatible with M-PHY 4.0 and UniPro 1.8
- Scalable AES-CTR/GCM/GMAC 10 to 100 Gbps
- AES high-speed and multi-purpose crypto engine (ECB, CTR, CBC, CFB, OFB, XTR, CCM, GCM, OMAC)
- High-speed and scalable AES-XTS engine
- INSIDE Secure Multi-Channel MACsec Engine v2
- INSIDE Secure Multi-Channel MACsec Engine v1
