Arkville provides a high-throughput line-rate agnostic conduit between FPGA hardware and GPP software. Using industry-standard AXI interfaces on the FPGA side and DPDK interfaces on the software API/ABI side, Arkville provides an exceptional “out-of-the-box” solution for both hardware and software teams.
Because Arkville was designed with the specific goal of accelerating and empowering DPDK, the performance is significantly higher than one of a naïve DMA implementation on an FPGA.
Arkville has both a hardware and software component. The hardware component is an IP core that resides in the FPGA, producing and consuming AXI streams of packets making ingress or egress. The software component is a DPDK PMD “net/ark”, the Arkville DPDK poll-mode driver.
Together, an Arkville solution looks to software like a “vanilla” line rate agnostic FPGA-based NIC (without any specific MAC). DPDK applications do not need to change significantly in order to enjoy the advantages of FPGA hardware acceleration.
- Line rate agnostic: Operates at any line rate, including 1/5/10/25/40/50/100/400 GbE
- Up to 150 Gbps and 120 Mpps with a contemporary PCIe Gen3x16 interface, Gen4 Ready
- 4 Physical Queue-Pairs (RX/TX) Standard; Up to 128 Physical Queue-Pairs
- FPGA Vendor Agnostic RTL
- Open-Source “net/ark” Arkville driver in DPDK 17.05
- Offload server cycles to FPGA gates
- Bring your FPGA-based packet processing solutions to market quickly
- Future proof your GPP/FPGA application with the DPDK and AXI standards
- Example designs:
- Four-Port, Four-Queue 10 GbE example (Arkville + 4x10 GbE MAC)
- Single-Port, Single-Queue 100 GbE example (Arkville + 1x100 GbE MAC)
- Available in encrypted or full source forms. Both versions include the elements needed for implementation, including a self-validating test bench.
Block Diagram of the DPDK-aware FPGA/GPP data mover IP Core