MIPI CSI2 rev 2.0 transmitter/controller for FPGA, with 8 lanes and 2.5Gbps per lane
Driver Drowsiness Detector
The logiDROWSINE is carefully partitioned between hardware and software to assure high performance and optimal utilization of the Xilinx Zynq-7000 AP SoC. The complete driver drowsiness SoC design, which consists of the logiDROWSINE, logiFDT and other IP cores, fits into the smallest Xilinx Zynq SoC and use only a single CPU core. It is prepackaged for the Xilinx Vivado Design Suite and IP deliverables include the software driver, documentation and technical support.
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