The AC2050 TDM over Packet IP core implements Circuit Emulation Services Interworking Functions (CES IWF) for 32 DS1/E1 TDM channels.
The AC2050 is available as an IP core, fully compliant with Altera® Qsys. The Qsys system integration tool saves significant time and effort in the FPGA design process by automatically generating interconnect logic to connect intellectual property (IP) functions and subsystems.
Evaluation of the AC2050 core is easily accomplished via the intuitive plug-and-play environment. An FPGA with on-chip CPU, Ethernet packet interfaces and the TDMoP core can be quickly built and simulated, and then tested on an eval board.
A complete wireless backhaul system can be created on a single FPGA by adding other functions from the Qsys IP core library. All interfaces to the TDMoP core are Qsys compliant to enable easy integration.
The AC2050 implements the SAToP and CESoPSN modes defined by IETF, MEF, MFA and ITU. These support transport of transparent DS1/E1 channels, or provide bandwidth efficient nx64 fractional channels.
The integrated DS1/E1 framers enable fault and performance monitoring, including test pattern insertion and loopback. The IP core supports Ethernet, VLAN, IP and MPLS PWE3 packet headers.
Each TDM channel can be configured independently for adaptive, differential or retiming clock recovery mode, and each channel may operate at a different clock rate.
The core is ideally prepared for new protocols or standards evolution due to its FPGA based design.
Evaluation systems are available for system level testing.
- TDM over Packet CES IWF for 32 DS1/E1 ports
- SAToP or CESoPSN transport mode selectable per channel (RFC4553 and RFC5086)
- Configurable amount of TDM data per packet
- Clock recovery mode selectable per channel: adaptive, differential or retiming mode
- RTP header for differential clock (RFC3550)
- Jitter and wander compliant to MEF18, ITU-T G.8261 and G.823 / G.824 for traffic interfaces
- Configurable jitter buffer size
- Extensive set of CES fault and performance monitoring points
- Integrated DS1/E1 framer with alarm, fault and performance monitoring, and support for loopbacks and PRBS maintenance functionality
- Integrated packet header processor for MAC addresses, VLAN tags, IP and MPLS PWE3 headers
- TDM interface to LIU at 1.544 or 2.048 Mb/s
- Qsys Avalon Streaming packet interface
- Qsys Avalon MM CPU interface
- DDR2 DRAM for jitter buffer
- FPGA target: Cyclone® IV or V
Block Diagram of the DS1/E1 TDM over Packet IP core