DSP-enhanced ARC EMxD and HS4xD processors provide combined RISC + DSP processing for computation intensive applications
For example, Release 15 of the 5G specification from the 3GPP – ITU standards organization has unified many of the wireless connectivity applications and has pushed the specifications of data rates above 1Gbps for mobile wireless devices.
As the majority of these mobile devices will be battery powered, modem SoC (baseband) developers face a very complex task of implementing higher performance data computation systems, but within the very tight power and area budgets required by the demanding consumer markets.
Synopsys’ extensive portfolio of DesignWare IP, including ARC Processors, offers a complete and wide range of IP cores to meet these requirements.
The Internet of Things (IoT) covers billions of connected devices in a wide range of applications, from remote sensors collating data at a very low data rate, wearables, smart connected devices in the home, neighborhood and industrial applications to automotive devices. Along with a broad set of applications there is a range of wireless communication standards and technologies.
Due to time to market, cost and ultra-low power consumption constraints, SoC developers generally look for single solution across multiple applications and standards. Synopsys offers an extensive portfolio of DesignWare IP, including programmable processors that can support multiple wireless communication standards on a single core, to meet a range of application requirements.
The DSP-enhanced DesignWare® ARC® EMxD and HS4xD Families of embedded 32-bit processors are based on the scalable ARCv2DSP Instruction Set Architecture (ISA). The DSP-enhanced ARC processor families support a broad portfolio of certified audio codecs and post-processing software from a range of popular standards including Dolby, DTS, Microsoft and SRS.
With patented configuration technology, the cores can be easily customized to meet any application requirement from ultra-small task-specific controllers robust application processors. Additionally, the extendible instruction set makes it possible for customers to add instructions and operations to provide additional acceleration and more efficient operation, resulting in highly differentiated designs that cannot be built with standard, off-the-shelf DSPs or CPUs.
These processors are also designed to be tolerant to high memory latencies. Compared to other solutions in the market, the impact of latency on the processor load is negligible, making the ARC processors the best solution for systems like video and graphics IP, where DDR memory is shared with other resources.
See Synopsys' portfolio of ARC codecs that are optimized for ARC processors with DSP capabilities.
Our interaction with devices in the home, at the workplace and in public is changing. In the past we used device interfaces like a keyboard, mouse, or touch screen. Now the trend is changing, with devices being developed to interact with humans via a human interface including voice, motion and vision. These human-machine interfaces are computationally intensive and use large, power-hungry processors, which greatly reduces battery life. To mitigate the power consumption of these larger processors, smaller, ‘wake-up’ cores are used to detect multiple sensor interface inputs and identify if a human interaction is about to begin, at which time it wakes up the bigger computation core.
he smaller wake up cores can also perform sensor fusion tasks by receiving input from multiple sensors and processing them. These processors require high computation capability to process the sensor input, while consuming minimal area and power for battery-operated devices.
Automobiles are the next generation of mobile connected devices with rapid advances being made in autonomous vehicles. These self-driving cars use a variety of technologies to gain 360 degree vision, both near, in the vehicle’s immediate vicinity, and far.
Automotive applications are very strict in terms of quality and maturity. Synopsys offers a broad portfolio of ASIL-B and ASIL-D certified ready DesignWare IP and processors.
View DSP-enhanced ARC EMxD and HS4xD processors provide combined RISC + DSP processing for computation intensive applications full description to...
- see the entire DSP-enhanced ARC EMxD and HS4xD processors provide combined RISC + DSP processing for computation intensive applications datasheet
- get in contact with DSP-enhanced ARC EMxD and HS4xD processors provide combined RISC + DSP processing for computation intensive applications Supplier
- High-performance ARC HS3x and HS4x processors are optimized for GHz+ operating speeds with minimum area and power consumption
- Compact, ultra-low power ARC EM processors and ASIL-Ready ARC EM Safety Island IP feature excellent code density
- Complete suite of development tools, ARC development systems and operating systems for embedded software application development
- ARC EV Processors are fully programmable and configurable IP cores that are optimized for embedded vision applications
- tRoot Hardware Secure Module with ARC SEM Security Processor
- DesignWare ARC EV72FS Embedded Vision Safety Processor with two vector processing units, ASIL B/C/D