DTMB Demodulator and Decoder IP (Silicon Proven)
This IP accepts one-path 10-bits samples, generated by an A/D converter sampling to an around (but not limited to ) 36.167MHz-centered IF or around (but not limited to ) 5.767 MHz-centered Low-IF signal, as digital input data. And this IP also accepts zero frequency digital input data. The input data is 2’s complementary format.
The sampling clock of A/D is assumed to be either 31.12MHz or 30.4MHz, which is a free-running clock, i.e, no need of feedback control from digital processing system. Down-conversion and I/Q separation for both IF and low-IF input is performed digitally inside the IP. Also a digital adjacent filter is implemented to potentially relax the requirement for external analog filters, therefore only one external SAW filter is required.
View DTMB Demodulator and Decoder IP (Silicon Proven) full description to...
- see the entire DTMB Demodulator and Decoder IP (Silicon Proven) datasheet
- get in contact with DTMB Demodulator and Decoder IP (Silicon Proven) Supplier