Low-power dual 10-bit DAC IP operating up to 160MS/s and using a single 1.2V supply.
Implemented in a 90nm process from TSMC.
The design provides high-speed operation, high-linearity and low-power dissipation.
Auxiliary circuits comprising a low-noise bandgap reference, voltage reference buffers (including external or internal decoupling as two separate options) and a biasing control circuitry to compensate for gain errors are also included to provide a complete DAC solution.
- 90nm Process, No Analog Options
- Dual 10-bit Current-Steering DAC
- Sampling Rate Up to 160MS/s
- Single 1.2V Supply
- Coarse and Fine Programmable Full-Scale Current
- Programmable Data Format
- Only 30mW Typ. at 160MS/s
- Only 27mW Typ. at 80MS/s
- DNL= 0.5LSB Typ., INL= ï¿½0.75LSB Typ.
- SNR= 60dB at FIN= 10MHz and 160MS/s
- SFDR= 64dB at FIN= 10MHz and 160MS/s
- THD= 61dB at FIN= 10MHz and 160MS/s
- Internal Voltage References
- Very Compact Die Area
- Detailed datasheet
- Integration guidelines
- Flatten netlist in standard format
- Physical layout in GDSII format
- Verilog/VHDL behavioral models
- Footprint in standard format
- Integration support services